Vlsi Research Papers 2015 Gmc

  • M. Bansal, Q. Khan, C. Shi, Average current mode control of multi-phase switching power converters, US 9,442,140, Sep. 13, 2016.

  • Q. Khan, S. Dhar, J. Zazzera, T. Sutton, Circuits and Methods for Driving Resonant Actuators, US 9,344,022, May 17, 2016.

  • Davinder Aggarwal, Vibhor Jain, Janakiraman VIRARAGHAVAN, “Automated design rule checking (DRC) test case generation”, US 8,875,064, Oct 28, 2014.

  • Davinder Aggarwal, Vaibhav A. RUPARELIA, Neha Singh, Janakiraman VIRARAGHAVAN, “Generic design rule checking (DRC) test case extraction”, US 9,292,652, Mar 22 2016.

  • C. Narathong and S. Aniruddhan, “Multi-mode Configurable Transmitter Circuit”, US 8,099,127, Jan. 17, 2012.

  • C. Narathong, S. Aniruddhan and W. Su, “Amplifier with Gain Expansion Stage”, US 8,035,443, Oct. 11, 2011.

  • B. Sun, S. Aniruddhan and S. Sridhara, “Method and Apparatus for Divider Unit Synchronization”, US 7,965,111, Jun. 25, 2011.

  • S. Aniruddhan, B. Sun, A. Jayaraman and G.S. Sahota, “Mixer with High Output Power Accuracy and Low Local Oscillator Leakage”, US 7,941,115, May 10, 2011.

  • C. Narathong and S. Aniruddhan, “Techniques for improving Balun Loaded-Q”, US 7,863,986, Jan. 4, 2011.

  • Q. Khan, S. Wadhwa, D. Tripathi, G.K. Sidhartha, K. Misri, PVT Variation Detection and Compensation Circuit, US 7495465, Feb. 24, 2009.

  • D. Tripathi, G.K. Sidhartha, Q. Khan, K. Misri, S. Wadhwa, US 7446592, PVT Variation Detection and Compensation Circuit, Nov. 4, 2008.

  • Q. Khan, G.K. Sidhartha, Sequence-independent Power-on Reset for Multi-Voltage Circuits, US 7432748, Oct. 7, 2008.

  • D. Tripathi, J. Banerjee, Q. Khan, Differential Receiver Circuit, US 7414462, Aug. 19, 2008.

  • Q. Khan, H. Fukazawa, T. Nandurkar, Charge Pump Circuit for High Side Drive Circuit and Driver Driving Voltage Circuit, US 7388422, Jun. 17, 2008.

  • G. K. Sidhartha, Q. Khan, D. Tripathi, S. Wadhwa, K. Misri, PVT Variation Detection and Compensation Circuit, US 7388419, Jun. 17, 2008.

  • N. Krishnapura(with I. Shpantzer et al.), “System and method for code division multiplexed optical communication”, US 7,167,651, Jan. 23, 2007.

  • Q. Khan, D. Tripathi, Transmission Line Driver Circuit, US 7292073, Nov. 6, 2007.

  • D. Tripathi, Q. Khan, K. Misri, Transmission Line Driver, US 7187197, Mar. 6, 2007.

  • S. Wadhwa, Q. Khan, K. Misri, D. Muhury, Digital Clock Frequency Doubler, US 7132863, Nov. 7, 2006.

  • Q. Khan, D. Tripathi, K. Misri, High Voltage Level Converter Using Low Voltage Devices, US 7102410, Sep. 5, 2006.

  • Q. Khan, S. Wadhwa, K. Misri, Bandgap Reference Circuit, US 7084698, Aug. 1, 2006.

  • Q. Khan, S. Wadhwa, K. Misri, Bidirectional Level Shifter, US 7061299, Jun, 13, 2006.

  • Q. Khan, S. Wadhwa, K. Misri, Single Supply Level Shifter, US 7009424, Mar. 7, 2006.

  • Shanthi Pavan, “Integrated circuit implementation for power and area efficient adaptive equalization”, US 7,142,596, Nov 28, 2006; jointly assigned to Indian Institute of Technology Madras and Vitesse Semiconductor, California.

  • N. Krishnapura(with I. Shpantzer et al.), “System and method for orthogonal frequency division multiplexed optical communication”, US 7,076,169, Jul. 11, 2006.

  • John S. Wang, Sudeep Bhoja, Shanthi Pavan, Hai Tao, “Method and apparatus for improved high-speed adaptive equalization”, US 7,003,228, Feb. 21, 2006.

  • Shanthi Pavan et al., “Mobility Compensation in MOS Integrated Circuits”, US 6,822,505, 23 Nov. 2004.

  • VTS registration page is NOW OPEN!

    Don’t miss VTS advanced registration rate. Register by April 10th, 2015.

    Register now!!

    The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, debug and repair of microelectronic circuits and systems.

    The VTS Program Committee invites original, unpublished paper submissions for VTS 2015Paper submissions should be complete manuscripts, up to six pages (inclusive of figures, tables, and bibliography) in a standard IEEE two-column format; papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status. On the title page, please include: author name(s) and affiliation(s), and the mailing address, phone number, and e-mail address of the contact author. A 50-word abstract and five keywords identifying the topic area are also required.

      VTS TOPICS

    • 2.5D, 3D and SiP Test
    • Analog, Mixed-Signal & RF Test
    • ATE Architecture & Software
    • ATPG & Compression
    • Built-In Self-Test (BIST)
    • Defect & Current Based Test
    • Defect and Fault Modeling, Defect based Fault Analysis
    • Delay & Performance Test
    • Dependability and Reliability
    • Design For Testability
    • Design Verification/Validation
    • Diagnosis and Debug
    • Embedded System & Board Test
    • Embedded Test Methods
    • Emerging Technologies Test
    • FPGA Test
    • Hardware Security
    • High Level System Testing
    • Memory Test and Repair
    • On-Line Test & Error Correction
    • Power and Thermal Issues in Test
    • System-on-Chip (SOC) Test
    • Test Economics/Test Quality
    • Test of Biomedical Devices
    • Test of High-Speed I/O
    • Test of MEMS
    • Test Resource Partitioning
    • Test Standards
    • Transients and Soft Errors

    Comments

    Leave a Reply

    Your email address will not be published. Required fields are marked *